ADSL is being widely deployed around the world as a major broadband Internet access technology. As the number of ADSL subscribers and the demand for bandwidth rapidly increase, it is highly desirable to provide a multiple-port ADSL solution that has a high density, low power, low gate count, and can be incorporated in a single chip for both central-office (CO) side and customer premises (CPE) side applications.
To try to obtain these features in a communications transceiver, a designer typically looks at many trade-offs associated with using various approaches to signal processing. Several prior art techniques have involved using a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA) to perform processing operations on the transceiver signal.
The DSP transceiver approach involves using a processor, either alone or in combination with a CPU, to execute microcode software in connection with the transceiver processing operations. This arrangement is used by Vitesse Semiconductor Corporation (see PCT WO 00/10297 and PCT WO 00/10281) in connection with their Network Processor product line, as well as Texas Instruments in their ADSL transceiver products (see “Programmable Implementations of xDSL Transceiver Systems”, IEEE Communications Magazine, May 2000). Additionally, Logic Devices Inc. has an approach involving a DSP in connection with a CPU (see U.S. Pat. No. 5,524,244), and Cirrus Logic has a dual DSP approach (see U.S. Pat. No. 6,081,783). As expressed in these references, a DSP based transceiver has the advantage of being easily upgradeable and customizable because the instructions are implemented in software. The down side of this approach is that the DSP can require more power, more time, and more gates than a dedicated ASIC where the instructions are hardwired into the design. Furthermore, as one moves to a multiple port design, the benefits of high density, low power, and low gate count become even more important.
A transceiver design involving only ASIC components will necessarily require at least one distinct logic core for every operation contemplated, resulting in a large gate count, and a difficult and costly feature upgrade path. As an example, Hilevel Technologies' approach involves an ASIC comprised of an array of functional cores, only one of which is operable at any time (see U.S. Pat. No. 6,157,051). This approach involves a series of separate collections of gates that are permanently wired, and the functional units are not capable of interrelation or even simultaneously operation.
Other approaches have addressed the relatively low efficiency of software processing, and the relatively unchangeable functions of hardware processing, to arrive at an approach involving FPGAs. For example, see “Configurable Computing: A Survey of Systems and Software,” Northwestern University, Department of ECE, Technical Report 1999). Additional approaches that teach the use of FPGAs to strike a balance between the benefits of software (DSP) and hardware (ASIC) can be seen in Ricoh Corporation's U.S. Pat. No. 6,182,206 B1, as well as Intel Corporation's U.S. Pat. No. 5,768,598. All of these approaches involve significant flexibility and relatively low power. However, the FPGA approach typically results in an undesirable quantity of unused gates, and a relatively slow speed due to reconfiguration time and the inherent slowness of a software design.
What is needed is a design that can obtain the flexibility of a programmable solution as well as the speed and size benefits of a dedicated IC solution.